The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A successive approximation register (SAR) analog-to-digital converter (ADC) converts an analog input (e.g., a waveform) into a discrete digital representation via a binary search through all possible quantization levels before finally converging upon a digital output for each conversion. A SAR ADC performs a successive approximation algorithm (sometimes referred to as “a binary search algorithm”) to provide a binary digital code. When the approximation is completed, the SAR ADC outputs an estimated digital output indicating the binary code. A SAR ADC includes a capacitive digital-to-analog converter (DAC), a comparator, and a logic module or circuit (e.g., a SAR circuit) that converts an analog input voltage into a digital code. A reference generator provides a reference voltage to the DAC. A range of output voltages (i.e., a resolution) of the DAC is controlled by the reference voltage.
The reference voltage typically varies during operation of the DAC. Such voltage variation causes inaccurate conversion of analog signal into a digital signal, errors at an output of the ADC, non-linear ADC output, etc. As one example, the reference voltage typically decreases from an initial steady-state value in each conversion cycle, for instance when more current is drawn by the DAC for most-significant-bit (MSB) conversion (referred to as an MSB phase). Typically, the reference voltage subsequently increases, for instance due to less current being drawn for least-significant-bit (LSB) conversion (referred to as an LSB phase). The reference voltage typically returns to the steady-state value as the conversion cycle nears completion. As another example, the amount of current drawn by the DAC varies based on the input voltage provided to the ADC for conversion.
Accordingly, SAR ADCs include a decoupling capacitor connected at an input of the DAC to stabilize the reference voltage. The area of the decoupling capacitor is large relative to a total area of the DAC. For example, the decoupling capacitor occupies 50% or more of the total area of the DAC. In some examples, the decoupling capacitor is more than 400 times larger than a total capacitor size of the capacitive DAC.